The present application claims priority under 35 U.S.C. xc2xa7119 to Korean Patent Application No. 99-50848, filed on Nov. 16, 1999, which is hereby incorporated by reference in its entirety for all purposes.
1. Field of the Invention
The present invention relates to a semiconductor device and fabrication method thereof, and more particularly to a ferroelectric capacitor and a method of forming the ferroelectric capacitor.
2. Description of the Related Art
Modern data processing systems require that a substantial portion of the information stored in memory be randomly accessible to ensure rapid access to such information. Due to the high speed operation of memories implemented in semiconductor technologies, ferroelectric random access memories(FRAMs) have been developed. FRAMs exhibit a significant advantage of being nonvolatile, which is achieved by virtue of the fact that a ferroelectric capacitor includes a pair of capacitor electrodes with a ferroelectric material therebetween which has two different stable polarization states which can be defined with a hysteresis loop depicted by plotting the polarization against applied voltage. The hysteresis loop characteristic may be varied depending on fabrication parameters of the FRAM.
FRAM fabrication methods include ferroelectric capacitor processes. Ferroelectric capacitor processes include plasma etching of electrode layers and a ferroelectric film interposed therebetween. Generation of electrical charge within the exposed layer during plasma etching is a well-known phenomena in the art. In particular, during FRAM fabrication, a capacitor stack (made of a lower electrode layer, a ferroelectric film and an upper electrode layer) exposed to plasma etching is subjected to plasma etching damage and electrical charge generation phenomenon occurs, thereby degrading the ferroelectric characteristic (hysteresis loop characteristic) of the ferroelectric film. The present inventors knew that due to the loading effect caused by the plasma characteristic, higher plasma potential is generated in the capacitor stack at outermost parts of the cell array region, as compared to at the cell array interior. Accordingly, plasma etching damage is mainly concentrated on the capacitor stack at outermost parts of the cell array region.
Due to such plasma damage at the outermost part of the cell array region, the ferroelectric characteristic of cell capacitors at the outermost parts of the cell array region is different than the ferroelectric characteristic of cell capacitors at the interior of the cell array region, as shown in FIG. 1. Comparing polarization level, the outermost cell capacitor has a significantly low polarization level as compared to the interior cell capacitor. Accordingly, a uniform and stable ferroelectric characteristic cannot be obtained throughout the cell array region, thereby reliable device performance cannot be secured.
Defects of the outermost cells of the cell array region originate because of the following two reasons. A first reason is generation of a damaged layer on the ferroelectric film. The other reason is charging of the capacitor stack. Because of these defects, the two stable polarization states of the ferroelectric film may become fixed at either one state or the other, resulting in reduction of the polarization level so that the cell cannot operate properly. Accordingly, there is a need for a method of forming a ferroelectric capacitor that is capable of preventing variation of ferroelectric characteristic.
The present invention is therefore directed to a ferroelectric capacitor and a method of fabrication thereof which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
Therefore, it is an object of the present invention to provide a method of forming a ferroelectric capacitor that can prevent degrading of the ferroelectric capacitor at outermost parts of a cell array region, and to thereby secure a stable ferroelectric characteristic throughout the cell array region.
It is another object of the present invention to provide a ferroelectric capacitor having a stable ferroelectric characteristic.
It is a feature of the present invention that a dummy cell capacitor is simultaneously formed at a dummy cell region provided at the periphery of the cell array region, when a cell capacitor is formed at a cell array region. Accordingly, the loading effect of the plasma etching process can be concentrated mainly on the dummy cell capacitor.
More particularly, in order to achieve the above-said objects of the present invention, a method of forming a ferroelectric capacitor includes providing a semiconductor substrate having a cell array region and a dummy region at a periphery of the cell array region; performing a device isolation process and defining a first active region in a selected portion of the cell array region; forming an interlayer insulating layer on an entire surface of the semiconductor substrate; forming a first contact plug, penetrating a selected portion of the interlayer insulating layer and being electrically connected to the first active region; forming a ferroelectric capacitor stack made of a lower electrode layer, a ferroelectric film and an upper electrode layer, in this order, on an entire surface of the interlayer insulating layer including the first contact plug; and plasma etching the capacitor stack and forming a ferroelectric capacitor to be electrically connected to the first contact plug at the cell array region, while concurrently forming a dummy ferroelectric capacitor at the dummy cell region.
Preferably, the device isolation process also defines a second active region in the dummy cell region of the substrate, and the forming of a first contact plug also includes forming a second contact plug to be electrically connected to the second active region through the interlayer insulating layer. At this time, the dummy ferroelectric capacitor is electrically connected to the second contact plug, such that a current path from the dummy ferroelectric capacitor to the second active region is generated.
The forming of an interlayer insulating layer on an entire surface of the semiconductor substrate includes forming a transistor on the first active region of the cell array region; forming a first insulating layer on the resultant structure having the transistor, to insulate the transistor; forming a bit line on the first insulating layer to be electrically connected to the first active region; and forming a second insulating layer on the second insulating layer and on the bit line. The bit line penetrates the first insulating layer and is electrically connected to the first active region on one side of the transistor, and the first contact plug penetrates the first and second insulating layers and is electrically connected to the first active region on another side of the transistor.
Herein, it is also preferable that the device isolation process also defines a second active region in the dummy cell region of the substrate, and the forming of a first contact plug also includes forming a second contact plug to be electrically connected to the second active region through the first and second insulating layers. The dummy ferroelectric capacitor is electrically connected to the second contact plug, such that a current path from the dummy ferroelectric capacitor to the second active region is generated.
In order to achieve the above described objects of the present invention, a method of forming a ferroelectric capacitor includes providing a semiconductor substrate having a cell array region and a dummy cell region at a periphery of the cell array region; performing a device isolation process and defining a first active region at the cell array region; forming a transistor on the first active region; forming a first insulating layer on the substrate and on the transistor; forming a bit line on the first insulating layer to be electrically connected to the first active region on one side of the transistor; forming a second insulating layer on the bit line and on the first insulating layer; forming a first contact plug in the second insulating layer, the first contact plug penetrating the second and first insulating layers and being electrically connected to the first active region on another side of the transistor; forming a ferroelectric capacitor stack made of a lower electrode layer, a ferroelectric film and an upper electrode layer in this order on an entire surface of the second insulating layer and on the first contact plug; and plasma etching the capacitor stack and forming a ferroelectric capacitor to be electrically connected to the first contact plug at the cell array region while concurrently forming a dummy ferroelectric capacitor at the dummy cell region, wherein a charging up phenomenon caused by plasma etching is concentrated on the second ferroelectric capacitor of the to dummy cell region.
It is preferable that the device isolation process also defines a second active region in the dummy cell region of the substrate, and the forming of a first contact plug also includes forming a second contact plug to be electrically connected to the second active region through the first and second insulating layers. The dummy ferroelectric capacitor is electrically connected to the second contact plug, such that a current path from the dummy ferroelectric capacitor to the second active region is generated, and the electrical charges generated within the dummy ferroelectric capacitor flow into the second active region of the dummy cell region through the second contact plug.
In order to achieve the above objects of the present invention, there is provided a ferroelectric capacitor including a semiconductor substrate having a cell array region and a dummy cell region provided at a periphery of the cell array region; a first active region formed at a selected portion of the cell array region of the semiconductor substrate; an interlayer insulating layer formed on an entire surface of the substrate; a first contact plug formed in a selected portion of the interlayer insulating layer to be electrically connected to the first active region; and a ferroelectric capacitor and a dummy ferroelectric capacitor formed on the interlayer insulating layer, the ferroelectric capacitor being formed over the cell array region to be electrically connected to the first contact plug.
The interlayer insulating layer can further comprise a transistor formed on the first active region, a first insulating layer formed on the transistor and on the substrate, a bit line formed on the first insulating layer and a second insulating layer formed on the first insulating layer and the bit line. The bit line penetrates the first insulating layer and is electrically connected to the substrate on one side of the transistor. The first contact plug penetrates a selected portion of the first and second insulating layers and is electrically connected to the first active region on another side of the transistor.
Preferably, the ferroelectric capacitor further includes a second active region in a selected portion of the dummy cell region wherein a second contact plug penetrates a selected portion of the interlayer insulating layer and is electrically connected to the second active region. The dummy ferroelectric capacitor is electrically connected to the second contact plug, such that an electrical path from the dummy ferroelectric capacitor to the second active region is generated.
It is an advantage of the present invention that plasma etching damage is mainly concentrated on the dummy cell region, and thus the outermost parts of the cell array region are substantially not subject to etching damage. Accordingly, ferroelectric capacitors with a stable ferroelectric characteristic can be obtained throughout the cell array region.
It is another advantage of the present invention that electrical charges generated on the dummy capacitor can easily flow out to the second active region formed at a semiconductor substrate of the dummy cell region through an electrical current path between the dummy cell capacitor and the second active region. Accordingly, plasma etching damage can be advantageously reduced.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.